- trace instruction
- команда трассировкисм. тж. tracer
Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. . 1998-2007.
Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. . 1998-2007.
Trace vector decoder — is a system that uses a microprocessor s trace mode to decode encrypted code just in time before it is executed and possibly re encrypt it after the execution. It can be used to enforce copy protections for some computer systems.Trace Vector in… … Wikipedia
Trace scheduling — is an optimization technique used in compilers for computer programs.A compiler often can, by rearranging its generated machine instructions for faster execution, improve program performance. Trace scheduling is one of many known techniques for… … Wikipedia
Instruction set simulator — An instruction set simulator (ISS) is a simulation model, usually coded in a high level programming language, which mimics the behavior of a mainframe or microprocessor by reading instructions and maintaining internal variables which represent… … Wikipedia
Instruction scheduling — In computer science, instruction scheduling is a compiler optimization used to improve instruction level parallelism, which improves performance on machines with instruction pipelines. Put more simply, without changing the meaning of the code, it … Wikipedia
Instruction step — An instruction step is a method of executing a computer program one step at a time to determine how it is functioning. This might be to determine if the correct program flow is being followed in the program during the execution or to see if… … Wikipedia
Very long instruction word — or VLIW refers to a CPU architecture designed to take advantage of instruction level parallelism (ILP). A processor that executes every instruction one after the other (i.e. a non pipelined scalar architecture) may use processor resources… … Wikipedia
Explicitly parallel instruction computing — (EPIC) is a term coined in 1997 by the HP Intel alliance [cite web url = http://www.hpl.hp.com/techreports/1999/HPL 1999 111.pdf title = EPIC: An Architecture for Instruction Level Parallel Processors accessdate = 2008 05 08 last = Schlansker and … Wikipedia
Centre D'Instruction À La Pacification Et À La Contre-Guérilla — Sommaire 1 École de guerre psychologique 2 CIPCG de Philippeville 3 CIPCG d Arzew 4 Bibliographie … Wikipédia en Français
Centre D'instruction À La Pacification Et À La Contre-guérilla — Sommaire 1 École de guerre psychologique 2 CIPCG de Philippeville 3 CIPCG d Arzew 4 Bibliographie … Wikipédia en Français
Centre d'Instruction a la Pacification et a la Contre-Guerilla — Centre d Instruction à la Pacification et à la Contre Guérilla Sommaire 1 École de guerre psychologique 2 CIPCG de Philippeville 3 CIPCG d Arzew 4 Bibliographie … Wikipédia en Français
Centre d'Instruction à la Pacification et à la Contre-Guérilla — Sommaire 1 École de guerre psychologique 2 CIPCG de Philippeville 3 CIPCG d Arzew 4 Bibliographie … Wikipédia en Français